Automatic Constraint Generation for Boundary Scan Interconnect Tests

This paper discusses an algorithm to automate the generation of constraints files by leveraging a simple extension to the device characteristic model. This extension consists of additional pin-level restriction data that defines the test constraints. While additional constraints based on the unique features of the design may still be required, the component-based constraints can be quickly determined and the corresponding file quickly generated by this process. All required design information is gathered from files already used in the interconnect test generation process. Since the pin-level restrictions apply to each instance of that component in the design, they will be declared in the component's characteristic model. The pin restriction information in the component characteristic models is the only information that will not be present in a typical test generation process. No other modifications to any files are required, which greatly reduces the effort required in generating the constraints.